From a8164ddfb5fd261ec266db11b881dae515ba184d Mon Sep 17 00:00:00 2001
From: liurunyu <lry9898@163.com>
Date: 星期五, 22 十一月 2024 16:42:06 +0800
Subject: [PATCH] 调整pom配置
---
pipIrr-platform/pipIrr-web/pipIrr-web-remote/src/main/java/com/dy/pipIrrRemote/rtuUpgrage/RtuUpgradeStateReceiverCtrl.java | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/pipIrr-platform/pipIrr-web/pipIrr-web-remote/src/main/java/com/dy/pipIrrRemote/rtuUpgrage/RtuUpgradeStateReceiverCtrl.java b/pipIrr-platform/pipIrr-web/pipIrr-web-remote/src/main/java/com/dy/pipIrrRemote/rtuUpgrage/RtuUpgradeStateReceiverCtrl.java
index f379023..897e5a7 100644
--- a/pipIrr-platform/pipIrr-web/pipIrr-web-remote/src/main/java/com/dy/pipIrrRemote/rtuUpgrage/RtuUpgradeStateReceiverCtrl.java
+++ b/pipIrr-platform/pipIrr-web/pipIrr-web-remote/src/main/java/com/dy/pipIrrRemote/rtuUpgrage/RtuUpgradeStateReceiverCtrl.java
@@ -317,6 +317,13 @@
if(!hasRunning){
cache.ugOverallState.allOver = true ;
}
+ if(cache.ugOverallState.allOver){
+ if(cache.ugRtuStateList != null && cache.ugRtuStateList.size() > 0){
+ for(UpgradeRtu rtu : cache.ugRtuStateList){
+ rtu.isOver = true ;
+ }
+ }
+ }
return hasRunning ;
}
}
--
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