From 5e31f7c1f3eaf5cfd3be0e5fc942aa78f3a4133c Mon Sep 17 00:00:00 2001 From: liurunyu <lry9898@163.com> Date: 星期二, 25 二月 2025 10:19:07 +0800 Subject: [PATCH] 修改下发缓存命令的等待逻辑，RTU上行数据后，使尽快发送下行命令。 --- pipIrr-platform/pipIrr-mw/pipIrr-mw-simulate-rtu/src/main/resources/config.xml | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/pipIrr-platform/pipIrr-mw/pipIrr-mw-simulate-rtu/src/main/resources/config.xml b/pipIrr-platform/pipIrr-mw/pipIrr-mw-simulate-rtu/src/main/resources/config.xml index fa87df5..1996da7 100644 --- a/pipIrr-platform/pipIrr-mw/pipIrr-mw-simulate-rtu/src/main/resources/config.xml +++ b/pipIrr-platform/pipIrr-mw/pipIrr-mw-simulate-rtu/src/main/resources/config.xml @@ -10,5 +10,5 @@ --> <base rtuAddr="532328000214"></base> <!-- --> - <tcpCl mwServerIp="192.168.40.132" mwServerPort="60000" connectTimeout="3000" /> + <tcpCl mwServerIp="192.168.40.166" mwServerPort="60000" connectTimeout="3000" /> </config> \ No newline at end of file -- Gitblit v1.8.0