From 1569cd94fdbc9081260d9f0ae13ca7a35d1bfb01 Mon Sep 17 00:00:00 2001
From: zhubaomin <zhubaomin>
Date: 星期四, 19 六月 2025 15:05:22 +0800
Subject: [PATCH] 优化读卡接口
---
pipIrr-platform/pipIrr-global/src/main/resources/mapper/UgRtuControllerMapper.xml | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/pipIrr-platform/pipIrr-global/src/main/resources/mapper/UgRtuControllerMapper.xml b/pipIrr-platform/pipIrr-global/src/main/resources/mapper/UgRtuControllerMapper.xml
index fd8a25f..37c93e5 100644
--- a/pipIrr-platform/pipIrr-global/src/main/resources/mapper/UgRtuControllerMapper.xml
+++ b/pipIrr-platform/pipIrr-global/src/main/resources/mapper/UgRtuControllerMapper.xml
@@ -140,10 +140,10 @@
AND ugCon.rtu_addr = #{rtuAddr,jdbcType=VARCHAR}
</if>
<if test="state != null and state == 1">
- AND ugCon.ug_state = 1
+ AND ugCon.ug_state = 2
</if>
<if test="state != null and state == 0">
- AND ugCon.ug_state != 1
+ AND ugCon.ug_state != 2
</if>
<if test="fail != null">
AND ugCon.ug_state = #{fail,jdbcType=INTEGER}
@@ -175,10 +175,10 @@
AND ugCon.rtu_addr = #{rtuAddr,jdbcType=VARCHAR}
</if>
<if test="state != null and state == 1">
- AND ugCon.ug_state = 1
+ AND ugCon.ug_state = 2
</if>
<if test="state != null and state == 0">
- AND ugCon.ug_state != 1
+ AND ugCon.ug_state != 2
</if>
<if test="fail != null">
AND ugCon.ug_state = #{fail,jdbcType=INTEGER}
--
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